NDLI: Towards optimized functional evaluation of SEE-induced failures in complex designs

Content Provider	IEEE Xplore Digital Library
Author	Alexandrescu, D. Costenaro, E.
Copyright Year	2012
Description	Author affiliation: iRoC Technologies, Grenoble, France (Alexandrescu, D.; Costenaro, E.)
Abstract	Single Event Effects strongly impact the reliability of electronic circuits and systems, requiring careful SER characterization and adequately sized mitigation strategy. The SER study aims at providing relevant information about the circuit behavior in the specified working environment, in terms of Functional Failures rates, criticality and so on. Ultimately, the error mitigation efforts are directed at improving the function of the circuit in the presence of SEE by either reducing the failure occurrence rate or the failure impact. However, when dealing with SEEs affecting highly sophisticated electronic designs, functional issues are one of the most complex aspects to reliably characterize. This paper aims at proposing and evaluating several fault characterization techniques, meant to approximate the functional failures induced by Single Event Upsets in complex circuits, very early in the design flow. The two main contributions of our efforts consist in a differential fault simulation approach based on standard simulation tools and a novel parallel, SEE-optimized, stand-alone simulation tool. Both methods accurately evaluate the immediate propagation of SEE-induced faults and predict the long-term behavior of the faulty circuit running a specified application. The works described in this paper also benefit from various optimization techniques targeting lower simulation costs (in terms of CPU and man-power) while preserving the accuracy of the results. Ultimately, the results of each method compare positively with reference data obtained from an exhaustive fault simulation campaign. This encouraging outcome suggests that we can reliably obtain highly informative functional error information while spending reasonable resources (CPU, man-power, time).
Starting Page	182
Ending Page	187
File Size	299924
Page Count	6
File Format	PDF
ISBN	9781467320825
e-ISBN	9781467320856
DOI	10.1109/IOLTS.2012.6313869
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Integrated circuit modeling Clocks Standards Vectors Computational modeling Logic gates Fault Simulation Functional De-Rating Soft Error Rate Single Event Upset
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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