NDLI: Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits

Content Provider	IEEE Xplore Digital Library
Author	El-Maleh, A.H. Daud, K.A.K.
Copyright Year	1963
Abstract	Due to current technology scaling trends, digital designs are becoming more sensitive to radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low-energy particle can flip the output of a gate, resulting in a soft error if it propagates to a circuit output. Thus, soft error tolerance has become an important criterion in digital system design. In this work, we propose a simulation-based approach to reduce the soft error probability of circuit failure in combinational logic circuits. The proposed method is based on maximizing the probability of logical masking when a soft error occurs. This maximization is done by extracting sub-circuits from an original multi-level circuit, and then re-synthesizing each extracted sub-circuit to increase fault masking against a single fault. We present a two-level synthesis scheme to maximize soft error masking on each extracted sub-circuit. This scheme provides a heuristic that finds the best set of cubes to cover the input patterns of an extracted sub-circuit. A Fast Extraction (FX) algorithm is used to enhance the area overhead of synthesized two-level sub-circuits. Experimental results on some MCNC combinational benchmarks show that, on average, a probability of circuit failure reduction of 32% is achieved compared to the original circuit. The average area overhead is 40% of the original circuit.
Sponsorship	IEEE Reliability Society
Starting Page	935
Ending Page	948
Page Count	14
File Size	1207763
File Format	PDF
ISSN	00189529
Volume Number	64
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Circuit faults Wires Fault tolerance Fault tolerant systems Combinational circuits Integrated circuit reliability soft errors Combinational circuit reliability fault tolerance single event transient single event upset
Content Type	Text
Resource Type	Article
Subject	Safety, Risk, Reliability and Quality Electrical and Electronic Engineering

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