NDLI: Architectural vulnerability aware checkpoint placement in a multicore processor

Content Provider	IEEE Xplore Digital Library
Author	Lotfi, A. Bayat, A. Safari, S.
Copyright Year	2012
Description	Author affiliation: School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran (Lotfi, A.; Bayat, A.; Safari, S.)
Abstract	As the system complexity increases, the failure probability increases substantially. Therefore, the system requires techniques for supporting fault tolerance. Checkpointing technique is widely used to reduce the execution time of long-running programs in presence of failures and enhancing the reliability of such systems. Several methods were studied thus far in order to determine the checkpointing interval which optimizes system performance. The crucial parameter in all of these solutions is system failure model which is primarily assumed as exponential or Weibull distributions. But, these models are not perfectly accurate since they fail to model the effect of soft errors. In this paper, we introduce a more realistic failure model based on the processors AVF. In addition, we propose three checkpoint placement methods with constant and variable intervals that determine suitable checkpoint places for the proposed failure model. Our experimental results show that our method, which is implementable on any multicore system, can find the suitable points in which checkpoints should be taken.
Starting Page	118
Ending Page	120
File Size	398665
Page Count	3
File Format	PDF
ISBN	9781467320825
e-ISBN	9781467320856
DOI	10.1109/IOLTS.2012.6313852
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Checkpointing Multicore processing Mathematical model Error analysis Processor scheduling Equations Computational modeling
Content Type	Text
Resource Type	Article

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