NDLI: Multi-channel digital SiPMs: Concept, analysis and implementation

Content Provider	IEEE Xplore Digital Library
Author	Mandai, S. Charbon, E.
Copyright Year	2012
Description	Author affiliation: Tech. Univ. Delft, Delft, Netherlands (Mandai, S.; Charbon, E.)
Abstract	This paper presents a comprehensive statistical analysis of timing resolution in a digital silicon photomultiplier (DSiPM) when multi timestamp is available. We look at the effect of dart count rate (DCR) on timing resolution in these devices as compared to analog silicon photomultipliers (A-SiPMs). The analysis includes photon detection efficiency (PDE), DCR, electrical jitter of the detector with a LYSO crystal. Timing resolution is analyzed utilizing a single timestamp or multiple timestamps. Simulation results show that D-SiPMs utilizing multiple timestamps (Multi-channel D-SiPM) can be more tolerant to DCR than those utilizing a single timestamp. The timing resolution is 13%, 20% and 40% better at 1000 detected photons, 200 ps rise time and 40 ns decay time of a LYSO scintillator, without DCR, with 1 MHz DCR and with 10 MHz DCR, respectively. Based on these findings, we propose new architectures to acquire multiple timestamps without sacrificing fill-factor. This paper also includes the implementation and characterization of 4 × 4 Multichannel D-SiPMs coupled with an array of 44ps LSB TDCs for coincidence detection of gamma rays. The pitch of the SiPMs is 800 μm and the number of pixels in one SiPM is 416. The pixel has a 57% fill factor with 121 ps timing resolution for a single photon. The SiPM timing resolution for single photon detection is 179 ps FWHM.
Sponsorship	IEEE Nucl. Plasma Sci. Soc
Starting Page	1840
Ending Page	1844
File Size	2482371
Page Count	5
File Format	PDF
ISBN	9781467320283
ISSN	10823654
e-ISBN	9781467320306
DOI	10.1109/NSSMIC.2012.6551429
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in