NDLI: A high resolution time-to-digital converter using two-level vernier delay line technique

Content Provider	IEEE Xplore Digital Library
Author	Li, G.H. Chou, H.P.
Copyright Year	2007
Abstract	This paper describes the design of time-to- digital converter ( TDC ) with two level Vernier delay line (VDL) , which is used to solve the problem of long conversion time in single level VDL and reduce the number of elements. The time interval to be measured between two pulse signals is separated into integral period part and non-integral period part by control circuit. Integral part is sent to counter, and non-integral parts are sent to the two level VDL. In the first VDL can get coarse resolution ( $T_{clk}/N$ ) , and the signals will be transmitted to the second VDL by the proposed interface circuit. Fine resolution $(Tclk/N^{2})$ can be gotten in the second VDL. Finally, readout circuit converts thermal code to binary code and do the subtraction to obtain the final results. The bias voltage of delay elements in VDL is controlled by DLL, this makes delay elements can stably provide two kinds of delay time for VDL. The circuit is realized with the process of TSMC CMOS 0.18 um 1P6M. 200 Mhz clock frequency is chosen in the circuit. From the simulation results, the conversion time is smaller than 5 clock periods, the maximum time can be measured is 75 ns. After the fine resolution is modified to 29.6 ps, the DNL is within -0.33LSB - +0.69LSB , and INLis within +0.47LSB - +1.08LSB.
Starting Page	276
Ending Page	280
File Size	306438
Page Count	5
File Format	PDF
ISBN	9781424409228
ISSN	10957863
DOI	10.1109/NSSMIC.2007.4436330
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay lines Delay effects Pulse measurements Time measurement Signal resolution Clocks Pulse circuits Counting circuits Binary codes Voltage control
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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