NDLI: Low-noise CMOS preamplifier-shaper for silicon drift detectors

Content Provider	IEEE Xplore Digital Library
Author	Gramegna, G. O'Connor, P. Rehak, P. Hart, S.
Copyright Year	1997
Description	Author affiliation: Brookhaven Nat. Lab., Upton, NY, USA (Gramegna, G.)
Abstract	We have designed a 16-channel preamplifier-shaper for particle tracking using silicon drift detectors (SDD). The preamplifier, which is optimized for a detector capacitance of 0.2-0.8 pF, uses two new circuit techniques to achieve a low noise (ENC 120 e-+62 e-/pF), high linearity (<0.5% to 50 fC), and good tolerance to process variations and temperature and power supply fluctuations. The circuit is continuously sensitive, has no digital signals on chip, and requires no external components or critical adjustments. The peaking time of the shaper is 50 nsec and the power dissipation, including an off-chip driver, is 6.5 mW/channel. The circuit is fabricated in 1.2 /spl mu/m CMOS and can accommodate detector leakage currents of up to 1.5 /spl mu/A. Although the circuit was developed for use with particle tracking detectors, these techniques are also well-suited for the design of lower-noise preamplifiers for high-resolution X-ray spectroscopy systems.
Starting Page	346
Ending Page	350
File Size	409029
Page Count	5
File Format	PDF
ISBN	0780335341
ISSN	10823654
DOI	10.1109/NSSMIC.1996.590985
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Detectors Particle tracking Preamplifiers Capacitance Circuit noise Noise shaping Linearity Temperature sensors Power supplies
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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