NDLI: Front-end interface of the SVD readout system for BELLE

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Electrical performance of the front end electronics system for the D0 silicon upgrade

Design and performance of beam test electronics for the PHENIX Multiplicity Vertex Detector

Front-end interface of the SVD readout system for BELLE

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Conference Author Index

Front-end interface of the SVD readout system for BELLE

Content Provider	IEEE Xplore Digital Library
Author	Ikeda, H. Tanaka, M. Matsuda, T. Fukunaga, C. Nobori, T. Saitoh, Y. Akamine, T. Inoue, M. Yamanaka, J. Mandai, M. Takeuchi, H. Kitta, T. Saitoh, M. Miyahara, S. Kamiya, M.
Copyright Year	1997
Description	Author affiliation: Nat. Lab. for High Energy Phys., Ibaraki, Japan (Ikeda, H.)
Abstract	The data-acquisition system for a Si micro-vertex detector of the BELLE experiment is described with special emphasis placed on the front-end circuits and their interfaces. The description includes a 128-channel preamplifier chip, a silicon-based double-sided hybrid card, and readout control chips for digital interfaces, which are discussed in terms of both architectural and operational aspects.
Starting Page	11
Ending Page	15
File Size	556775
Page Count	5
File Format	PDF
ISBN	0780335341
ISSN	10823654
DOI	10.1109/NSSMIC.1996.590875
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-11-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Preamplifiers Large scale integration Circuit noise Detectors Prototypes Fabrication Control systems Silicon Size control Communication system control
Content Type	Text
Resource Type	Article

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