NDLI: High-performance memory interface architecture for high-definition video coding application

Content Provider	IEEE Xplore Digital Library
Author	Joon-Ho Song Doo Hyun Kim Do-Hyung Kim Shi Hwa Lee
Copyright Year	2010
Description	Author affiliation: Samsung Advanced Institute of Technology, Samsung Electronics, Yongin, Korea (Joon-Ho Song; Doo Hyun Kim; Do-Hyung Kim; Shi Hwa Lee)
Abstract	This paper proposes new memory interface architecture to overcome huge SDRAM bandwidth requirements of video decoders. To improve the memory efficiency, tile based memory access method and pixel cache are adopted. In addition to large data transfer cycle, extra overhead cycles takes great part of the heavy memory bandwidth requirement. The overhead cycles are caused by two reasons- the one is due to row-activation overhead of SDRAM and the other is due to redundant data transfer for motion compensation. The row-activation overhead is incurred frequently because of the block by block memory access pattern of standard video decoding algorithms. By using the tile based memory access method, the row-activation overhead can be reduced significantly. The redundant data transfer overhead is due to the 6-tap FIR filtering for the motion compensation while H.264/AVC decoding. We reduced the redundant memory transfer overhead by adopting the reference pixel cache, which is tightly coupled with multi-frame reference picture and the memory structure of the tile based memory access method. Experimental results show that the proposed method can decode 1920 × 1080, 30 frame per second H.264/AVC main profile bitstream in real time with only about 90MHz SDRAM clock. Compared to the conventional linear memory access system, the proposed method reduces about 6 times of SDRAM bandwidth. We also expect the proposed method will reduce power consumption because the SDRAM bandwidth requirement and the number of row-activation overhead are significantly reduced.
Starting Page	3745
Ending Page	3748
File Size	248516
Page Count	4
File Format	PDF
ISBN	9781424479924
ISSN	15224880
e-ISBN	9781424479948
e-ISBN	9781424479931
DOI	10.1109/ICIP.2010.5653435
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-26
Publisher Place	Hong Kong
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SDRAM Pixel Automatic voltage control Bandwidth Motion compensation Decoding Tiles Cache memories SDRAM bandwidth compression H.264/AVC Video coding processing
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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