NDLI: A compact single-pass architecture for hysteresis thresholding and component labeling

Content Provider	IEEE Xplore Digital Library
Author	Al Najjar, M. Karlapudi, S. Bayoumi, M.
Copyright Year	2010
Description	Author affiliation: The Center for Advanced Computer Studies, University of Louisiana at Lafayette, USA (Al Najjar, M.; Karlapudi, S.; Bayoumi, M.)
Abstract	Hysteresis thresholding offers enhanced edge/object detection in the presence of noise. However, due to its recursive nature, it requires a lot of memory and execution time. Thus, it is restricted and sometimes totally avoided in streaming processors with limited memory. We propose an efficient architecture coupling hysteresis thresholding with component labeling and feature extraction in a single pass over the image pixels. The operations are performed on the fly while recycling labels to avoid additional passes for handling candidate pixels and extracting object features. Moreover, only one row of compact labels is buffered. Hence, the execution speed of the algorithm is increased and the memory requirements are drastically reduced when compared to state of the art techniques. When implemented on FPGA, this technique promises to offer even more speed up and efficient resource utilization.
Starting Page	101
Ending Page	104
File Size	342032
Page Count	4
File Format	PDF
ISBN	9781424479924
ISSN	15224880
e-ISBN	9781424479948
e-ISBN	9781424479931
DOI	10.1109/ICIP.2010.5652676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-26
Publisher Place	Hong Kong
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel Feature extraction Image edge detection Hysteresis Labeling Memory management Streaming media streaming processors connected component labeling feature extraction hysteresis thresholding
Content Type	Text
Resource Type	Article

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