NDLI: Slipstream execution mode for CMP-based multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Ibrahim, K.Z. Byrd, G.T. Rotenberg, E.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA (Ibrahim, K.Z.; Byrd, G.T.; Rotenberg, E.)
Abstract	Scalability of applications on distributed shared-memory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism yields diminishing returns or even degrades performance. When increasing concurrency is futile, we propose an additional mode of execution, called slipstream mode, that instead enlists extra processors to assist parallel tasks by reducing perceived overheads. We consider DSM multiprocessors built from dual-processor chip multiprocessor (CMP) nodes with shared L2 cache. A task is allocated on one processor of each CMP node. The other processor of each node executes a reduced version of the same task. The reduced version skips shared-memory stores and synchronization, running ahead of the true task. Even with the skipped operations, the reduced task makes accurate forward progress and generates an accurate reference stream, because branches and addresses depend primarily on private data. Slipstream execution mode yields two benefits. First, the reduced task prefetches data on behalf of the true task. Second, reduced tasks provide a detailed picture of future reference behavior, enabling a number of optimizations aimed at accelerating coherence events, e.g., self-invalidation. For multiprocessor systems with up to 16 CMP nodes, slipstream mode outperforms running one or two conventional tasks per CMP in 7 out of 9 parallel scientific benchmarks. Slipstream mode is 12-19% faster with prefetching only and up to 29% faster with self-invalidation enabled.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Architecture
Starting Page	179
Ending Page	190
File Size	471938
Page Count	12
File Format	PDF
ISBN	0769518710
ISSN	15300897
DOI	10.1109/HPCA.2003.1183536
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-02-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concurrent computing Parallel processing Scalability Degradation Prefetching Performance gain Acceleration Coherence Multiprocessing systems Character generation
Content Type	Text
Resource Type	Article

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