NDLI: Mini-threads: increasing TLP on small-scale SMT processors

Content Provider	IEEE Xplore Digital Library
Author	Redstone, J. Eggers, S. Levy, H.
Copyright Year	2003
Description	Author affiliation: Washington Univ., St. Louis, MO, USA (Redstone, J.; Eggers, S.; Levy, H.)
Abstract	Several manufacturers have recently announced the first simultaneous-multithreaded processors, both as single CPU and as components of multi-CPU chips. All are small scale, comprising only two to four thread contexts. A significant impediment to the construction of larger-scale SMT is the register file size required by a large number of contexts. This paper introduces and evaluates mini-threads, a simple extension to SMT that increases thread-level parallelism without the commensurate increase in register file size. A mini-threaded SMT CPU adds additional per-thread state to each hardware context; an application executing in a context can create mini-threads that will utilize its own per-thread state, but share the context's architectural register set. The resulting performance will depend on the benefits of additional TLP compared to the costs of executing mini-threads with fewer registers. Our results quantify these factors in detail and demonstrate that mini-threads can improve performance significantly, particularly on small-scale, space-sensitive CPU designs.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Architecture
Starting Page	19
Ending Page	30
File Size	399279
Page Count	12
File Format	PDF
ISBN	0769518710
ISSN	15300897
DOI	10.1109/HPCA.2003.1183521
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-02-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surface-mount technology Registers Hardware Yarn Pipelines Parallel processing Throughput Application software Manufacturing processes Impedance
Content Type	Text
Resource Type	Article

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