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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lei Chen Dropsho, S. Albonesi, D.H. |
| Copyright Year | 2003 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA (Lei Chen) |
| Abstract | To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundamental limit to improving ILP is data dependences among instructions. If data dependence information is available at run-time, there are many uses to improve ILP. Prior published examples include decoupled branch execution architectures and critical instruction detection. In this paper, we describe an efficient hardware mechanism to dynamically track the data dependence chains of the instructions in the pipeline. This information is available on a cycle-by-cycle basis to the microengine for optimizing its performance. We then use this design in a new value-based branch prediction design using available register value information (ARVI). From the use of data dependence information, the ARVI branch predictor has better prediction accuracy over a comparably sized hybrid branch predictor With ARVI used as the second-level branch predictor the improved prediction accuracy results in a 12.6% performance improvement on average across the SPEC95 integer benchmark suite. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on Comput. Architecture |
| Starting Page | 65 |
| Ending Page | 76 |
| File Size | 365273 |
| Page Count | 12 |
| File Format | |
| ISBN | 0769518710 |
| ISSN | 15300897 |
| DOI | 10.1109/HPCA.2003.1183525 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-02-12 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Registers Microprocessors Application software Parallel processing Runtime Accuracy Out of order Read-write memory Computer architecture Computer science |
| Content Type | Text |
| Resource Type | Article |
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