NDLI: High-level and hierarchical test sequence generation

Content Provider	IEEE Xplore Digital Library
Author	Jervan, G. Peng, Z. Goloubeva, O. Reorda, M.S. Violante, M.
Copyright Year	2002
Description	Author affiliation: Embedded Syst. Lab., Linkoping Univ., Sweden (Jervan, G.; Peng, Z.)
Abstract	Test generation at the gate-level produces high-quality tests but is computationally expensive in the case of large systems. Recently, several research efforts have investigated the possibility of devising test generation methods and tools to work on high-level descriptions. The goal of these methods is to provide the designers with testability information and test sequences in the early design stages. The cost for generating test sequences in the high abstraction levels is often lower than that for generating test sequences at the gate-level, with comparable or even higher fault coverage. This paper first analyses several high-level fault models in order to select the most suitable one for estimating the testability of circuits by reasoning on their behavioral descriptions and for guiding the test generation process at the behavioral level. We assess then the effectiveness of high-level test generation with a simple ATPG algorithm, and present a novel high-level hierarchical test generation approach to improve the results obtained by a pure high-level test generator.
Sponsorship	IEEE Comput. Soc. Tech. Council on Test Technol. IEEE Comput. Soc. Tech. Committee on Design Autom
Starting Page	169
Ending Page	174
File Size	638298
Page Count	6
File Format	PDF
ISBN	0780376552
DOI	10.1109/HLDVT.2002.1224448
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-29
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults Automatic test pattern generation System testing Automatic testing Hardware design languages Embedded system Laboratories Costs System-on-a-chip
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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