NDLI: An effective and flexible approach to functional verification of processor families

Content Provider	IEEE Xplore Digital Library
Author	Malandain, D. Palmen, P. Taylor, M. Aharoni, M. Arbetman, Y. Arbetman, Y.
Copyright Year	2002
Description	Author affiliation: STMicroelectronics, Rousset, France (Malandain, D.)
Abstract	Functional verification is one of the most critical stages of microprocessor design. Its goal is to achieve the maximum level of confidence in the conformance of a processor design to its specification. A powerful methodology is necessary in order to cope with the major technical challenge which is posed by functional verification of a processor, and which stems from the vast state space that must be verified. This need becomes even more crucial when faced with the concurrent verification of several processor families. We describe a strategy for verification of several designs, which allows for maximum sharing of resources and knowledge among the verification projects, thus resulting in a significant increase in the efficiency of verification and in an associated reduction in the time required to verify a new design.
Sponsorship	IEEE Comput. Soc. Tech. Council on Test Technol. IEEE Comput. Soc. Tech. Committee on Design Autom
Starting Page	93
Ending Page	98
File Size	590013
Page Count	6
File Format	PDF
ISBN	0780376552
DOI	10.1109/HLDVT.2002.1224435
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-29
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing State-space methods Buildings Microprocessors Process design Silicon Registers Reservoirs Vehicle dynamics Random number generation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in