NDLI: Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

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Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

An RT-level fault model with high gate level correlation

A novel methodology for hierarchical test generation using functional constraint composition

Use of constraint solving in order to generate test vectors for behavioral validation

Behavioral-level test vector generation for system-on-chip designs

An approach to functional testing of VLIW architectures

A new method for on-line state machine observation for embedded microprocessors

Verification of in-order execution in pipelined processors

Silicon debug of a co-processor array for video applications

Interface based hardware/software validation of a system-on-chip

Hardware/software co-debugging for reconfigurable computing

Functional verification of an embedded network component by co-simulation with a real network

Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS)

Simulation strategy after model checking: experience in industrial SOC design

An approach to high-level synthesis system validation using formally verified transformations

On statistical behavior of branch coverage in testing behavioral VHDL models

Variable size analysis and validation of computation quality

Code simulation concept for S/390 processors using an emulation system

Formal operator testability methods for behavioral-level DFT using value ranges

System level testability analysis using Petri nets

High level fault simulation: experiments and results on ITC'99 benchmarks

On choosing test criteria for behavioral level hardware design verification

Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators

Refining abstract equivalence analysis for embedded system design

Toward automated abstraction for protocols on branching networks

Data flow based cache prediction using local simulation

Checking temporal properties under simulation of executable system descriptions

Compilation-based software performance estimation for system level design

Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations

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