NDLI: Combining HoL-blocking avoidance and differentiated services in high-speed interconnects

Content Provider	IEEE Xplore Digital Library
Author	Yebenes, P. Escudero-Sahuquillo, J. Gomez, C. Garcia, P.J. Alfaro, F.J. Quiles, F.J. Duato, J.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sytems, Univ. of Castilla-La Mancha, Albacete, Spain (Yebenes, P.; Escudero-Sahuquillo, J.; Gomez, C.; Garcia, P.J.; Alfaro, F.J.; Quiles, F.J.) \|\| Dept. of Comput. Eng., Politec. de Valencia, Spain (Duato, J.)
Abstract	Current high-performance platforms such as Datacenters or High-Performance Computing systems rely on highspeed interconnection networks able to cope with the ever-increasing communication requirements of modern applications. In particular, in high-performance systems that must offer differentiated services to applications which involve traffic prioritization, it is almost mandatory that the interconnection network provides some type of Quality-of-Service (QoS) and Congestion-Management mechanism in order to achieve the required network performance. Most current QoS and Congestion-Management mechanisms for high-speed interconnects are based on using the same kind of resources, but with different criteria, resulting in disjoint types of mechanisms. By contrast, we propose in this paper a novel, straightforward solution that leverages the resources already available in InfiniBand components (basically Service Levels and Virtual Lanes) to provide both QoS and Congestion Management at the same time. This proposal is called CHADS (Combined HoL-blocking Avoidance and Differentiated Services), and it could be applied to any network topology. From the results shown in this paper for networks configured with the novel, cost-efficient KNS hybrid topology, we can conclude that CHADS is more efficient than other schemes in reducing the interferences among packet flows that have the same or different priorities.
Starting Page	1
Ending Page	10
File Size	223780
Page Count	10
File Format	PDF
e-ISBN	9781479959761
DOI	10.1109/HiPC.2014.7116874
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-17
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Topology Network topology Quality of service Switches Ports (Computers) Proposals Routing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Efficient Queuing Schemes for HoL-Blocking Reduction in Dragonfly Topologies with Minimal-Path Routing

Towards an SDN network control application for differentiated traffic routing

Efficient Routing Mechanisms for Dragonfly Networks

IODET: A HoL-blocking-aware Deterministic Routing Algorithm for Direct Topologies

Switch folding: Network-on-Chip routers with time-multiplexed output ports

Analyzing Packet-Level Routing in Data Centers

Towards Software Defined SpaceWire Networks

SDN-RADAR: Network troubleshooting combining user experience and SDN capabilities

A novel network architecture for data center

Combining HoL-blocking avoidance and differentiated services in high-speed interconnects

Similar Documents

Efficient Queuing Schemes for HoL-Blocking Reduction in Dragonfly Topologies with Minimal-Path Routing

Towards an SDN network control application for differentiated traffic routing

Efficient Routing Mechanisms for Dragonfly Networks

IODET: A HoL-blocking-aware Deterministic Routing Algorithm for Direct Topologies

Switch folding: Network-on-Chip routers with time-multiplexed output ports

Analyzing Packet-Level Routing in Data Centers

Towards Software Defined SpaceWire Networks

SDN-RADAR: Network troubleshooting combining user experience and SDN capabilities

A novel network architecture for data center

Combining HoL-blocking avoidance and differentiated services in high-speed interconnects