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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Charif-Rubial, A.S. Oseret, E. Noudohouenou, J. Jalby, W. Lartigue, G. |
| Copyright Year | 2014 |
| Description | Author affiliation: Normandie Univ., Caen, France (Lartigue, G.) || Exascale Comput. Res. Lab., France (Charif-Rubial, A.S.; Oseret, E.; Noudohouenou, J.; Jalby, W.) |
| Abstract | Most of today's performance analysis tools are focused on issues occurring at multi-core and communication level. However there are several reasons why an application may not correctly behave in terms of performance at the core level. For a significant part, loops in industrial applications are limited by the quality of the code generated by the compiler and do not always fully benefit from the available computing power of recent processors. For instance, when the compiler is not able to vectorize loops, up to a 8x factor can be lost. It is essential to first validate the core level performance before focusing on higher level issues. This paper presents the CQA tool, a loop-centric code quality analyzer based on a simplified unicore architecture performance modeling and on quality metrics. The tool analyzes the quality of the code generated by the compiler. It provides high level metrics along with human understandable reports that relates to source code. Our performance model assumes that all data are resident in the first level cache. It provides architectural bottlenecks and an estimation of the number of cycles spent in each iteration of a given innermost loop. Our modeling and analyses are statically done and requires no execution or recompilation of the application. We show practical examples of situations where our tool is able to provide very valuable information leading to a performance gain. |
| Starting Page | 1 |
| Ending Page | 10 |
| File Size | 1064460 |
| Page Count | 10 |
| File Format | |
| e-ISBN | 9781479959761 |
| DOI | 10.1109/HiPC.2014.7116904 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-12-17 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Program processors Computer architecture Measurement Pipelines Registers Analytical models Estimation static analysis performance evaluation performance modeling vectorization |
| Content Type | Text |
| Resource Type | Article |
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