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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Penaranda, R. Gomez, C. Gomez, M.E. Lopez, P. Duato, J. |
| Copyright Year | 2012 |
| Abstract | In large parallel computers routing is a key design point to obtain the maximum possible performance out of the interconnection network. Routing can be classified into two categories depending on the number of routing options that a packet can use to go from its source to its destination. If the packet can only use a single predetermined path then the routing is deterministic, whereas if several paths are possible it is adaptive. It is a well-known fact that adaptive routing usually outperforms deterministic routing; but in this paper we take the challenge of developing a HOL-blocking-aware deterministic routing algorithm that can obtain a similar or even better performance than adaptive routing, while decreasing its implementation complexity and providing some inherent advantages to deterministic routing such as in-order delivery of packets. In this large computers regular direct topologies are widely-used, so in this paper we focus on meshes and tori. |
| Starting Page | 702 |
| Ending Page | 703 |
| File Size | 272064 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781467345651 |
| ISSN | 15219097 |
| e-ISBN | 9780769549033 |
| DOI | 10.1109/ICPADS.2012.103 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-12-17 |
| Publisher Place | Singapore |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Routing Topology Network topology Adaptive systems Switches Algorithm design and analysis Multiprocessor interconnection HoL Blocking topology routing algorithm |
| Content Type | Text |
| Resource Type | Article |
| Subject | Hardware and Architecture |
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