NDLI: Hardware efficient design of speed optimized power stringent Application Specific Processor

Content Provider	IEEE Xplore Digital Library
Author	Sengupta, A. Sedaghat, R. Zhipeng Zeng
Copyright Year	2009
Description	Author affiliation: Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada (Sengupta, A.; Sedaghat, R.; Zhipeng Zeng)
Abstract	New standards in communication, multimedia and signal processing have challenged the researchers to formalize the design methodology of an optimized Application Specific Processor (ASP) where the performance requirement should meet operational constraints like speed, chip area and power consumption. In this paper we describe a novel design approach to design a hardware efficient speed optimized power stringent application specific processor customized for a desired high performance. We initiate the design approach with the mathematical model of the application with strict operating constraints as specifications and finally describe our design at register transfer level. The proposed approach is capable for designing an ASP which is efficient not only in terms of hardware area but also contradictory parameters like speed and power consumption. To demonstrate our design approach for this power limited speed optimized ASP we selected a sample function as our application.
Starting Page	173
Ending Page	176
File Size	774601
Page Count	4
File Format	PDF
ISBN	9781424458141
e-ISBN	9781424458165
DOI	10.1109/ICM.2009.5418662
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-19
Publisher Place	Morocco
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Design optimization Application specific processors Energy consumption Communication standards Multimedia communication Signal processing Design methodology Constraint optimization Mathematical model power stringent Design approach Application Specific Processor speed optimized
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A graph based processor model for retargetable code generation

Multi parametric optimized architectural synthesis of an application specific processor

A hierarchical design of an application-specific instruction set processor for high-throughput FFT

Synthesis of application-specific highly-efficient multi-mode systems for low-power applications

Power efficient semi-automatic instruction encoding for application specific instruction set processors

Instruction subsetting: Trading power for programmability

An ASIP instruction set optimization algorithm with functional module sharing constraint

Reducing processor energy consumption by compiler optimization

Spread spectrum pre-processor ASIC design: a case study

Hardware efficient design of speed optimized power stringent Application Specific Processor

Similar Documents

A graph based processor model for retargetable code generation

Multi parametric optimized architectural synthesis of an application specific processor

A hierarchical design of an application-specific instruction set processor for high-throughput FFT

Synthesis of application-specific highly-efficient multi-mode systems for low-power applications

Power efficient semi-automatic instruction encoding for application specific instruction set processors

Instruction subsetting: Trading power for programmability

An ASIP instruction set optimization algorithm with functional module sharing constraint

Reducing processor energy consumption by compiler optimization

Spread spectrum pre-processor ASIC design: a case study

Hardware efficient design of speed optimized power stringent Application Specific Processor