NDLI: A graph based processor model for retargetable code generation

Content Provider	IEEE Xplore Digital Library
Author	Van Praet, J. Lanneer, D. Goossens, G. Geurts, W. De Man, H.
Copyright Year	1996
Description	Author affiliation: IMEC, Leuven, Belgium (Van Praet, J.; Lanneer, D.; Goossens, G.; Geurts, W.; De Man, H.)
Abstract	Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity the parallelism and all architectural peculiarities of an embedded processor In this paper; the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.
Starting Page	102
Ending Page	107
File Size	677205
Page Count	6
File Format	PDF
ISBN	0818674245
ISSN	10661409
DOI	10.1109/EDTC.1996.494133
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-03-11
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Application specific processors Digital signal processing Hardware Application software Design optimization Processor scheduling Consumer electronics Multimedia systems Multimedia communication
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Code generation for embedded processors with complex instructions

New application-specific processors.

A Transformation-Based Approach for Storage Optimization

Methods for retargetable DSP code generation

Multi parametric optimized architectural synthesis of an application specific processor

Address Code Optimization Exploiting Code Scheduling in DSP Applications

Hardware efficient design of speed optimized power stringent Application Specific Processor

Efficient scheduling of DSP code on processors with distributed register files

Retargetable Code Optimization for Predicated Execution

A graph based processor model for retargetable code generation

Similar Documents

Code generation for embedded processors with complex instructions

New application-specific processors.

A Transformation-Based Approach for Storage Optimization

Methods for retargetable DSP code generation

Multi parametric optimized architectural synthesis of an application specific processor

Address Code Optimization Exploiting Code Scheduling in DSP Applications

Hardware efficient design of speed optimized power stringent Application Specific Processor

Efficient scheduling of DSP code on processors with distributed register files

Retargetable Code Optimization for Predicated Execution

A graph based processor model for retargetable code generation