NDLI: Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Content Provider	IEEE Xplore Digital Library
Author	Xaioyao Liang Brooks, D.
Copyright Year	2006
Description	Author affiliation: Div. of Eng. & Appl. Sci., Harvard Univ., Cambridge, MA (Xaioyao Liang; Brooks, D.)
Abstract	Design variability due to die-to-die and within-die process variations has the potential to significantly reduce the maximum operating frequency and the effective yield of high-performance microprocessors in future process technology generations. One serious manifestation of this increased variability is a reduction in the mean frequency of fabricated chips due to fluctuations in device characteristics causing reduced circuit performance. In this paper, we propose to mitigate the impact of variations through variable-latency register files and execution units which are key architectural components that may encounter variability problems. We also illustrate the importance of closing the gap in expected delay of these distinct structures. A post fabrication test and configuration strategy is proposed. We find that 23% mean frequency improvement with an average IPC loss of 3% (and never exceeding 5% for worst case chips) is possible for the 65nm technology node by properly adopting the proposed schemes
Sponsorship	IEEE TC-uARCH ACM SIGMICRO
Starting Page	504
Ending Page	514
File Size	640333
Page Count	11
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Microarchitecture Delay Circuits Microprocessors Fluctuations Transistors Frequency estimation Pipelines Radio frequency
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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