NDLI: Dataflow Predication

Content Provider	IEEE Xplore Digital Library
Author	Smith, A. Nagarajan, R. Sankaralingam, K. McDonald, R. Burger, D. Keckler, S.W. McKinley, K.S.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci., Texas Univ., Austin, TX (Smith, A.; Nagarajan, R.; Sankaralingam, K.; McDonald, R.; Burger, D.; Keckler, S.W.; McKinley, K.S.)
Abstract	Predication facilitates high-bandwidth fetch and large static scheduling regions, but has typically been too complex to implement comprehensively in out-of-order micro architectures. This paper describes dataflow predication, which provides per-instruction predication in a dataflow ISA, low predication computation overheads similar to VLIW ISAs, and low complexity out-of-order issue. A two-bitfield in each instruction specifies whether an instruction is predicated, in which case, an arriving predicate token determines whether an instruction should execute. Dataflow predication incorporates three features that reduce predication overheads. First, dataflow predicate computation permits computation of compound predicates with virtually no overhead instructions. Second, early mispredication termination squashes in-flight instructions with false predicates at any time, eliminating the overhead of falsely predicated paths. Finally, implicit predication mitigates the fanout overhead of dataflow predicates by reducing the number of explicitly predicated instructions, by predicating only the heads of dependence chains. Dataflow predication also exposes new compiler optimizations - such as disjoint instruction merging and path-sensitive predicate removal - for increased performance of predicated code in an out-of-order design
Sponsorship	IEEE TC-uARCH ACM SIGMICRO
Starting Page	89
Ending Page	102
File Size	200613
Page Count	14
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.17
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Instruction sets Out of order Switches Microarchitecture VLIW Computer aided instruction Optimizing compilers Merging Size control Dynamic scheduling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Appears in the Proceedings of the 39 th Annual IEEE/ACM International Symposium on Microarchitecture Dataflow Predication

Static scheduling for out-of-order instruction issue processors

A performance comparison of several superscalar processor models with a VLIW processor

Region-based compilation: an introduction and motivation

Deconstructing commit

Speculative trace scheduling in VLIW processors

Compiling on Horizon

Control Flow Optimization Via Dynamic Reconvergence Prediction

Instruction pre-processing in trace processors

Dataflow Predication

Similar Documents

Appears in the Proceedings of the 39 th Annual IEEE/ACM International Symposium on Microarchitecture Dataflow Predication

Static scheduling for out-of-order instruction issue processors

A performance comparison of several superscalar processor models with a VLIW processor

Region-based compilation: an introduction and motivation

Deconstructing commit

Speculative trace scheduling in VLIW processors

Compiling on Horizon

Control Flow Optimization Via Dynamic Reconvergence Prediction

Instruction pre-processing in trace processors

Dataflow Predication