NDLI: A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Content Provider	IEEE Xplore Digital Library
Author	Mohamood, F. Healy, M.B. Lim, S.K. Lee, H.-H.S.
Copyright Year	2006
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA (Mohamood, F.; Healy, M.B.; Lim, S.K.; Lee, H.-H.S.)
Abstract	Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, power-hungrier designs. To battle the ever-aggravating power consumption, modern microprocessor designers or researchers propose and apply aggressive power-saving techniques in the form of clock-gating and/or power-gating in order to operate the processor within a given power envelope. These techniques, however, often lead to high-frequency current variations, which can stress the power delivery system and jeopardize reliability due to inductive noise (L(di/dt)) in the power supply network. To counteract these issues, modern microprocessors are designed to operate under the worst-case current assumption by deploying adequate decoupling capacitance. With the trend of lower supply voltage and increased leakage power and current consumption, designing a processor for the worst case is becoming less appealing. In this paper, we propose a new dynamic inductive-noise controlling mechanism at the microarchitectural level that limit the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt controller is the first that takes the processor's floorplan as well as its power-pin distribution into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times with an average performance overhead of 4.0%
Sponsorship	IEEE TC-uARCH ACM SIGMICRO
Starting Page	3
Ending Page	14
File Size	428629
Page Count	12
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process control Process design Microprocessors Power system reliability Voltage Microarchitecture Power system dynamics Energy consumption Clocks Stress
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable 2D and 3D Microprocessors

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design (2006)

Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

Variability and energy awareness: a microarchitecture-level perspective

Evaluating design tradeoffs in on-chip power management for CMPs

Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization

Reliability-aware SOC voltage islands partition and floorplan

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Similar Documents

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable 2D and 3D Microprocessors

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design (2006)

Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors

Variability and energy awareness: a microarchitecture-level perspective

Evaluating design tradeoffs in on-chip power management for CMPs

Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization

Reliability-aware SOC voltage islands partition and floorplan

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design