NDLI: Low-power sub-threshold design of secure physical unclonable functions

Content Provider	IEEE Xplore Digital Library
Author	Lin, Lang Holcomb, Dan Krishnappa, Dilip Kumar Shabadi, Prasad Burleson, Wayne
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering and Computer Science, University of California, Berkeley (Holcomb, Dan) \|\| Department of Electrical and Computer Engineering, University of Massachusetts, Amherst (Lin, Lang; Krishnappa, Dilip Kumar; Shabadi, Prasad; Burleson, Wayne)
Abstract	The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depends on minute uncontrollable process variations, a low supply voltage can benefit PUFs by providing high sensitivity to variations and low power consumption as well. Motivated by this, we explore the feasibility of sub-threshold arbiter PUFs in 45nm CMOS technology. By modeling process variations and interconnect imbalance effects at the post-layout design level, we optimize the PUF supply voltage for the minimum power-delay product and investigate the trade-offs on PUF uniqueness and reliability. Moreover, we demonstrate that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks. Our final 64-stage sub-threshold PUF design only needs 418 gates and consumes 0.047pJ energy per cycle, which is very promising for low-power wireless sensing and security applications.
Starting Page	43
Ending Page	48
File Size	910458
Page Count	6
File Format	PDF
ISBN	9781424485888
DOI	10.1145/1840845.1840855
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Security Reliability Integrated circuit modeling Delay Logic gates Latches Analytical models embedded system security Physical unclonable function sub-threshold circuits RFID
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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