NDLI: PASAP: Power aware structured ASIC placement

Content Provider	IEEE Xplore Digital Library
Author	Chakraborty, Ashutosh Pan, David Z.
Copyright Year	2010
Description	Author affiliation: ECE Department, University of Texas at Austin, Austin, Texas, USA (Chakraborty, Ashutosh; Pan, David Z.)
Abstract	Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineering (NRE) costs and turn-around-time but suffer from higher power consumption and lower performance. Power reduction for structured ASICs uses extensive clock and supply power-down of unused circuitry and use of low power devices. However, due to the limited granularity of power-down, physical design (specially placement) should be performed to maximize the components that can be powered down. In this paper, we present the first placement algorithm to specifically target this problem. Our tool, PASAP (Power Aware Structured ASIC Placement), minimizes the clock and leakage power by maximizing the fraction of the structured ASIC that can be powered down or disconnected from clock tree. On a set of large benchmark designs, PASAP reduces clock and leakage power by 32% and 17% respectively compared to prior structured ASIC placement tool RegPlace [1] incurring 17% penalty in wirelength and 30% longer runtime.
Starting Page	395
Ending Page	400
File Size	606903
Page Count	6
File Format	PDF
ISBN	9781424485888
DOI	10.1145/1840845.1840933
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Tiles Clocks Application specific integrated circuits Random access memory Algorithm design and analysis Benchmark testing Capacitance structured ASICs low power placement regular fabrics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

PASAP: power aware structured ASIC placement

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Clock routing for structured ASICs with via-configurable fabrics

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Relocatable and resizable SRAM synthesis for via configurable structured ASIC

Rapid prototyping on a structured ASIC fabric

Power aware placement for FPGAs with dual supply voltages

Rapid diagnostics of an ASIC IP block using dynamic laser scanning

Design of a single layer programmable Structured ASIC library

PASAP: Power aware structured ASIC placement

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