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Lowpower sub-threshold design of secure physical unclonable functions
| Content Provider | CiteSeerX |
|---|---|
| Author | Lin, Lang |
| Description | The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depends on minute uncontrollable process variations, a low supply voltage can benefit PUFs by providing high sensitivity to variations and low power consumption as well. Motivated by this, we explore the feasibility of sub-threshold arbiter PUFs in 45nm CMOS technology. By modeling process variations and interconnect imbalance effects at the post-layout design level, we optimize the PUF supply voltage for the minimum power-delay product and investigate the trade-offs on PUF uniqueness and reliability. Moreover, we demonstrate that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks. Our final 64-stage sub-threshold PUF design only needs 418 gates and consumes 0.047pJ energy per cycle, which is very promising for low-power wireless sensing and security applications. |
| File Format | |
| Language | English |
| Publisher Institution | in ISLPED, 2010 |
| Access Restriction | Open |
| Subject Keyword | Side-channel Analysis Attack Process Variation Chip Identification Security Application Low Power Consumption Cmos Technology Minimum Power-delay Product Puf Uniqueness High Sensitivity Physical Unclonable Function Design Optimization Sub-threshold Arbiter Pufs Minute Uncontrollable Process Variation Interconnect Imbalance Effect Secure Physical Unclonable Function Post-layout Design Level Sub-threshold Design Puf Supply Voltage Final 64-stage Sub-threshold Puf Design Unpredictable Nature Low Supply Voltage Wireless Sensing |
| Content Type | Text |
| Resource Type | Article |
