NDLI: A way-halting cache for low-energy high-performance systems

Content Provider	IEEE Xplore Digital Library
Author	Chuanjun Zhang Vahid, F. Jun Yang Najjar, W.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA, USA (Chuanjun Zhang)
Abstract	Caches contribute to much of a microprocessor system's power and energy consumption. We have developed a new cache architecture, called a way-halting cache, that reduces energy while imposing no performance overhead. Our way-halting cache is a four-way set-associative cache that stores the four lowest-order bits of all ways' tags into a fully associative memory, which we call the halt tag array. The look-up in the hall tag array is done in parallel with, and is no slower than, the set-index decoding. The hall tag array pre-determines which tags cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has an additional feature of using static logic only, rather than dynamic logic used in highly associative caches. We provide data from experiments on 17 benchmarks drawn from MediaBench and Spec 2000, based on our layouts in 0.18 micron CMOS technology, On average, 55% savings of memory-access related energy were obtained over a conventional four-way set-associative cache. We show that energy savings are greater than previous methods, and nearly twice that of highly-associative caches, while imposing no performance overhead and only 2% cache area overhead.
Sponsorship	ACM SIGDA IEEE Circuits and Syst. Soc
Starting Page	126
Ending Page	131
File Size	558128
Page Count	6
File Format	PDF
ISBN	1581139292
DOI	10.1109/LPE.2004.240851
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Logic arrays Energy consumption CMOS logic circuits Computer science Power engineering and energy Embedded computing Microprocessors Decoding Costs Permission
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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