NDLI: Custom instruction filter cache synthesis for low-power embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Vivekanandarajah, K. Srikanthan, T.
Copyright Year	2005
Description	Author affiliation: Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore (Vivekanandarajah, K.; Srikanthan, T.)
Abstract	Filter cache has been shown to substantially reduce the power consumption in instruction memory hierarchy. Filter cache achieves energy savings due to the locality found in the frequent tiny loops, which are application dependent. In this paper we show that tuning filter cache to the needs of a particular application can save power and energy. Beside, a simple loop profiler directed methodology to deduce the optimal or near-optimal filter cache is proposed, without having to simulating all possible combinations of cache parameters from the specified space. Our experiments with MediaBench benchmark suite shows that the proposed methodology results in up to 49% energy reduction by tuning the filter cache. Moreover, the proposed filter cache tuning is done with the loop characteristics of the application, which in most cases are readily made available.
Starting Page	151
Ending Page	157
File Size	168238
Page Count	7
File Format	PDF
ISBN	0769523617
ISSN	10746005
DOI	10.1109/RSP.2005.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-08
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Filters Embedded system Energy consumption Costs Cache memory Computer aided instruction Embedded computing High performance computing Power engineering computing Power engineering and energy
Content Type	Text
Resource Type	Article
Subject	Computer Science

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