NDLI: Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

Content Provider	IEEE Xplore Digital Library
Author	Deming Chen Cong, J.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA (Deming Chen; Cong, J.)
Abstract	This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high supply voltage (high-Vdd) or a low supply voltage (low-Vdd). We carry out the clustering procedure with the guarantee that the delay of the circuit under the general delay model is optimal, and in the meantime, logic blocks on the non-critical paths can be driven by low-Vdd to save power. We explore a set of dual-Vdd combinations to find the best ratio between low-Vdd and high-Vdd to achieve the largest power reduction. Experimental results show that our clustering algorithm can achieve power savings by 20.3% on average compared to the clustering result for an FPGA with a single high-Vdd. To our knowledge, this is the first work on dual-Vdd clustering for FPGA architectures.
Sponsorship	ACM SIGDA IEEE Circuits and Syst. Soc
Starting Page	70
Ending Page	73
File Size	349300
Page Count	4
File Format	PDF
ISBN	1581139292
DOI	10.1109/LPE.2004.240787
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Delay Field programmable gate arrays Clustering algorithms Algorithm design and analysis Integrated circuit interconnections Permission Computer science Low voltage Logic circuits Logic design
Content Type	Text
Resource Type	Article

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