NDLI: Total power optimization through simultaneously multiple-V/sub DD/ multiple-V/sub TH/ assignment and device sizing with stack forcing

Content Provider	IEEE Xplore Digital Library
Author	Hung, W. Xie, Y. Vijaykrishnan, N. Kandemir, M. Irwin, M.J. Tsai, Y.
Copyright Year	2004
Description	Author affiliation: Embedded & Mobile computing Design Center, Pennsylvania State Univ., University Park, PA, USA (Hung, W.; Xie, Y.; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J.; Tsai, Y.)
Abstract	In this paper, we present an algorithm for the minimization of total power consumption via multiple V/sub DD/ assignment, multiple V/sub TH/ assignment, device sizing and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded in genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are given for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier and a 32bit carry adders. From the experimental results, we show that the combination of four low power techniques is the effective way to achieve low power budget.
Sponsorship	ACM SIGDA IEEE Circuits and Syst. Soc
Starting Page	144
Ending Page	149
File Size	466365
Page Count	6
File Format	PDF
ISBN	1581139292
DOI	10.1109/LPE.2004.240886
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Energy consumption Genetic algorithms Power dissipation Circuits Algorithm design and analysis Minimization Equations Threshold voltage Permission Mobile computing
Content Type	Text
Resource Type	Article

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Total Power Optimization through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing

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