NDLI: 56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

Content Provider	IEEE Xplore Digital Library
Author	Chen, J.H.-C. Waskiewicz, C. Fan, S.S.-C. Halle, S. Chiew-seng Koay Yongan Xu Saulnier, N. Chia-Hsun Tseng Yunpeng Yin Mignot, Y. Beard, M. Morris, B. Horak, D. Mignot, S. Shobha, H. Sankarapandian, M. van der Straten, O. Kelly, J.J. Canaperi, D. Mclellan, E. Boye, C. Levin, T. Juntao Li Demarest, J. Choi, S. Huang, E. Liemann, L. Haran, B. Arnold, J.C. Colburn, M. Clevenger, L. Spooner, T.
Copyright Year	2012
Description	Author affiliation: IBM T. J. Watson Research Center, 1101 Kitchawan Road, Route 134, Yorktown Height, NY 10598, USA (Huang, E.) \|\| STMicroelectronics Inc., 257 Fuller Road, Albany, New York 12203 USA (Mignot, Y.; Mignot, S.) \|\| IBM Microelectronics Center, 2070 Route 52, Hopewell Junction NY 12533, USA (Choi, S.; Clevenger, L.) \|\| IBM in Albany Nano Science & Technology Research Center, 257 Fuller Road, IBM Corp., NY 12203, USA (Chen, J.H.-C.; Waskiewicz, C.; Fan, S.S.-C.; Halle, S.; Chiew-seng Koay; Yongan Xu; Saulnier, N.; Chia-Hsun Tseng; Yunpeng Yin; Beard, M.; Morris, B.; Horak, D.; Shobha, H.; Sankarapandian, M.; van der Straten, O.; Kelly, J.J.; Canaperi, D.; Mclellan, E.; Boye, C.; Levin, T.; Juntao Li; Demarest, J.; Liemann, L.; Haran, B.; Arnold, J.C.; Colburn, M.; Spooner, T.)
Abstract	This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.
Starting Page	1
Ending Page	3
File Size	948537
Page Count	3
File Format	PDF
ISBN	9781467311380
e-ISBN	9781467311373
e-ISBN	9781467311366
DOI	10.1109/IITC.2012.6251637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Copper Lithography Dielectrics Tungsten
Content Type	Text
Resource Type	Article

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