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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shyng-Tsong Chen Tae-Soo Kim Seo-woo Nam Lafferty, N. Chiew-Seng Koay Saulnier, N. Wenhui Wang Yongan Xu Duclaux, B. Mignot, Y. Beard, M. Yunpeng Yin Shobha, H. Van der Straten, O. Ming He Kelly, J. Colburn, M. Spooner, T. |
| Copyright Year | 2013 |
| Description | Author affiliation: Samsung Electron., Albany, NY, USA (Tae-Soo Kim; Beard, M.) || GLOBALFOUNDRIES, Albany, NY, USA (Seo-woo Nam; Wenhui Wang; Ming He) || STMicroelectron., Albany, NY, USA (Duclaux, B.; Mignot, Y.) || IBM, Albany Nano-Technol. Center, Albany, NY, USA (Shyng-Tsong Chen; Lafferty, N.; Chiew-Seng Koay; Saulnier, N.; Yongan Xu; Yunpeng Yin; Shobha, H.; Van der Straten, O.; Kelly, J.; Colburn, M.; Spooner, T.) |
| Abstract | For sub-64nm pitch interconnects build, it is beneficial to use Self Aligned Double Patterning (SADP) scheme for line level patterning. Usually a 2X pitch pattern was printed first, followed by a Sidewall Image Transfer (SIT) technique to create the 1X pitch pattern. A block lithography process is then used to trim this pattern to form the actual designed pattern. In this paper, 48nm and 45nm pitch SADP build will be used as examples to demonstrate the SADP patterning scheme. General discussions about this patterning scheme will be provided including: 1) the process flow of this technique, 2) benefits of the technique vs. pitch split approach, 3) the design impact and limitation, and 4) the extendability to smaller line pitch build. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 1681571 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781479904389 |
| e-ISBN | 9781479904402 |
| DOI | 10.1109/IITC.2013.6615589 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-06-13 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Shape Metals Bidirectional control Lithography Dielectrics Resistance Leakage currents |
| Content Type | Text |
| Resource Type | Article |
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