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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chen, F. Huang, E. Shinosky, M. Angyal, M. Kane, T. Wang, Y. Kolics, A. |
| Copyright Year | 2010 |
| Description | Author affiliation: IBM Microelectronics, 52 Hopewell Junction, NY 12533 (Angyal, M.; Kane, T.; Wang, Y.) || IBM Microelectronics, 1000 River Street, Essex Junction, VT, 05452 (Chen, F.; Shinosky, M.) || IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598, USA (Huang, E.) || Lam Research Corporation, Fremont, CA (Kolics, A.) |
| Abstract | As the current-carrying capability of a copper line is reduced due to interconnect dimension shrinkage, self-aligned CoWP metal-cap has been reported to be helpful to improve degraded electromigration (EM) reliability. However, adoption of this new metal cap in general further exacerbates the already problematic low-k dielectric TDDB reliability at 32nm and beyond. This paper provides a comparative study of ULK conduction mechanisms over a wide range of temperature (30 ºC to 295 ºC) and TDDB acceleration kinetics at 125 ºC for Cu interconnects with and without CoWP metal cap at 32nm technology. It was found that adding CoWP didn't change the fundamental ULK leakage conduction mechanism and TDDB kinetics if its process was optimized. Comparable leakage and TDDB performance were achieved with an optimized CoWP process. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 470987 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424476763 |
| e-ISBN | 9781424476787 |
| DOI | 10.1109/IITC.2010.5510693 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-06-06 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Copper Dielectrics Voltage Microelectronics Degradation Temperature distribution Kinetic theory Testing Leakage current Stress |
| Content Type | Text |
| Resource Type | Article |
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