NDLI: 3D large scale integration technology using Wafer-on-Wafer (WOW) stacking

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2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)

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2013 IEEE International Interconnect Technology Conference - IITC

2012 IEEE International Interconnect Technology Conference

2011 IEEE International Interconnect Technology Conference

2010 IEEE International Interconnect Technology Conference

Table of contents

3D system design: A case for building customized modular systems in 3D

A 3D interconnect system for large biosensor array and CMOS signal-processing IC integration

CVD Co and its application to Cu damascene interconnections

A key of self-formed barrier technique for reliability improvement of CU dual damascene interconnects

Interface effect on mn-containing self-formed barrier formation with extreme low-k dielectric integration

Structural effects on Chip Package Interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip-chip package

A new enhancement layer to improve copper interconnect performance

The improvement of electrical programmable fuse with salicide-block dielectric film in 40nm CMOS Technology

Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

A BEOL multilevel structure with ultra low-k materials (k ≤ 2.4)

Development, characterization and integration of a novel boron nitride process for application as a Cu diffusion barrier

Porous low k structural design to meet next generation interconnect needs

Robust multi-level RC design corners for 32/28nm advanced mobile SoC

Ultimate-low-k SiOCH film (k=3D1.3) with sufficient modulus (>5 GPa) and ultra-high thermal stability formed by low-temperature pulse-time-modulated neutral-beam-enhanced CVD

Conformal deposition of electroless barrier and seed layers in TSV with Au nano particle catalyst

Microprobing the mechanics of complex interconnect structures

AC conductance modeling and analysis of graphene nanoribbon interconnects

Evolutionary and revolutionary interconnect technologies for performance enhancement of subthreshold circuits

A study of signal integrity issues in through-silicon-via-based 3D ICs

Etching process scalability and challenges for ULK materials

Molecular design of ultra-low-k hybrid glasses

Function through structure: An atomistic view on the additive action at copper/electrolyte interfaces

Link between silica-metal agglomeration and high porosity ultra-low k scratch formation during Chemical Mechanical Polishing

Direct CMP process with advanced ELK for 45 nm half pitch interconnects

CMP process optimization for improved compatibility with advanced metal liners

Phase change memory: Development progress and system opportunities

Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters

MEMS technology using back-end of line processes in CMOS LSI

A CMOS compatible back end MEMS switch for logic functions

Small grain and twin characterization in sub-100 nm Cu interconnects using the conical dark-field technique in the transmission electron microscope

Damage characterization of low-k layers through Cu damascene process using monoenergetic positron beams

A comparative study of ULK conduction mechanisms and TDDB characteristics for Cu interconnects with and without CoWP metal cap at 32nm technology

Quantifying LER to predict its impact on BEOL TDDB reliability at 20nm ½ pitch

Low resistance W-contact for 32-nm node devices and beyond

A modified berman model for the prediction of time-dependent dielectric breakdown (TDDB) characteristics of low-k/ULK interconnect dielectrics from dual-voltage ramp dielectric breakdown (DVRDB) test

Three-dimensional characterization of crystalline grains in sub-100 nm Cu lines by Transmission Electron Microtomography

Spin-on dielectric liner TSV for 3D wafer level packaging applications

Low resistance wiring and 2Xnm void free fill with CVD Ruthenium liner and $DirectSeed^{TM}$ copper

Pt vias for high temperature MEMS interconnects

An efficient 3D Green's function approach for fast impedance extraction of interconnects and spiral inductors in CMOS RF/Millimeter-wavelength circuits

Improving Cu line Rs control using feed-forward information for CMP endpointing

Inhibition of enhanced Cu oxidation on ruthenium

Characterization of self-formed Ti-based barrier layers in Cu(Ti)/dielectric-layer samples using X-ray Photoelectron Spectroscopy

Mechanical properties of hydrogenated amorphous silicon carbide thin films

Minimization of plasma ashing damage to OSG low-k dielectrics

Bandwidth, delay and energy aware optimization of global interconnects for many-core architectures

On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators

Lead-free flip chip solution for 40 nm extreme low-k interconnect system

Capturing intrinsic impact of low-k dielectric stacks and packaging materials on mechanical integrity of Cu/low-k interconnects

3D TSV integration technology challenges for high volume production from fabless supply chain aspect

Electrical evaluation of 130-nm MOSFETs with TSV proximity in 3D-SIC structure

Temperature dependent electrical characteristics of through-si-via (TSV) interconnections

Development of low temperature dielectrics down to 150°C for multiple TSVs structure with Wafer-on-Wafer (WOW) technology

Robust spin-on glass gap-fill process technology for sub-30nm interlayer dielectrics

Demonstration of a reliable high-performance and yielding Air gap interconnect process

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

Path-finding for integration of porous SiOCH films (k∼2.5) in system-LSIs

Highly manufacturable ELK integration technology with metal hard mask process for high performance 32nm-node interconnect and beyond

Cu - based catalysts can make CMOS compatible Si nanowires: Toward reconfigurable interconnects

Networked-nanographite wire grown on SiO2 dielectric without catalysts using metal-photoemission-assisted Plasma-enhanced CVD

Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices

3D large scale integration technology using Wafer-on-Wafer (WOW) stacking

Recent advances in submicron alignment 300 mm copper-copper thermocompressive face-to-face wafer-to-wafer bonding and integrated infrared, high-speed FIB metrology

Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding

Reliability and ultra-low temperature bonding of high density large area arrays with Cu/Sn-Cu interconnects for 3D integration

Elementary process of electromigration at metal nanojunctions in the ballistic regime

Cap layer and grain size effects on electromigration reliability in Cu/low-k interconnects

Impact of oxygen on Cu surface for highly reliable low-k/Cu interconnects with CuSiN and Ti-based barrier metal

Highly reliable 45-nm-half-pitch Cu interconnects incorporating a Ti/TaN multilayer barrier

2009 IEEE International Interconnect Technology Conference

2008 International Interconnect Technology Conference

2007 IEEE International Interconnect Technology Conferencee

2006 International Interconnect Technology Conference

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)

Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)

Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461)

Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)

Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)

Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102)

3D large scale integration technology using Wafer-on-Wafer (WOW) stacking

Content Provider	IEEE Xplore Digital Library
Author	Ohba, T.
Copyright Year	2010
Description	Author affiliation: The University of Tokyo, 2-11-16 Yayoi, Bunkyo-ku, Tokyo 113-8656, Japan (Ohba, T.)
Abstract	Wafer-scale three-dimensional (3D) technologies, so-called Wafer-on-Wafer (WOW), beyond post-scaling for high-density integration are discussed. WOW module technologies consisting of wafer thinning, stacking, TSV (Through-Silicon-Via) interconnects, and packaging are described. No degradation for advanced 35-nm SRAM logic and FRAM devices was observed with ultra-thinning below 10-μm for 300-mm and 200-mm wafers. Production-worthy die yield due to wafer stacking and a comparison of critical scaling for future manufacturability are presented.
Starting Page	1
Ending Page	3
File Size	1061137
Page Count	3
File Format	PDF
ISBN	9781424476763
e-ISBN	9781424476787
DOI	10.1109/IITC.2010.5510747
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large scale integration Stacking Random access memory Through-silicon vias Packaging Degradation Logic devices Ferroelectric films Nonvolatile memory Manufacturing
Content Type	Text
Resource Type	Article

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