NDLI: Integrated Reliability Workshop

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2013 IEEE International Integrated Reliability Workshop Final Report

2012 IEEE International Integrated Reliability Workshop Final Report

2011 IEEE International Integrated Reliability Workshop Final Report

Wafer Level Reliability

Scaling to the final frontier: Reliability challenges in sub 20 nm technologies

Separating NBTI and PBTI effects on the degradation of Ring Oscillator frequency

On the PBTI degradation of pMOSFETs and its impact on IC lifetime

Cryogenic to room temperature effects of NBTI in high-k PMOS devices

On the microscopic limit of the reaction-diffusion model for the negative bias temperature instability

Technology variability and product design implications

Experimentally based methodology for charge pumping bulk defect trapping correction

Modeling of DCIV recombination currents using a multistate multiphonon model

Recent trends in CMOS reliability: From individual traps to circuit simulations

When does a circuit really fail?

Reliability analysis of enhancement-mode GaN MIS-HEMT with gate-recess structure for power supplies

Reliability and degradation mechanism of 0.25 µm AlGaN/GaN HEMTs under RF stress conditions

User verify and disturb mechanisms in a 65nm flash FPGA

Electron paramagnetic resonance studies of interlayer dielectrics

Constant voltage electromigration testing

Effects of current density on electromigration resistance trace analysis

Inline process characterization and control for robust BEOL reliability

Effects of pre-stress on hot-carrier degradation of N-channel MOSFETs

An advanced RF-CV method as a powerful characterization tool for the description of HC induced defect generation at microscopic level

Hot-carrier and recovery effect on p-channel lateral DMOS

Reliability degradation of MOS transistors originated from plasma process-induced charging of circuit blocks and detected with fWLR methods

TDDB characterization of BST capacitors exhibiting bimodal Weibull distributions

On-chip circuit for massively parallel BTI characterization

Impact of STI stress on hot carrier degradation in 5V NMOSFET

A new degradation mechanism of gate oxide reliability due to "extrinsic" responses of Qbd along rough "bird's-beak" frontline

Generation of single-and double-charge electron traps in tunnel oxide of flash memory cells under Fowler-Nordheim stress

The effect of fluorine implant on NBTI behaviour in BCD-processes

TCAD-based failure analysis and modeling of pit formation in GaN HEMTs

A practical approach to modeling product performance degradation and assigning lifetime reliability guard band

Impact of gate length and gate oxide thickness on the relationship of FN-stress induced degradation parameters

Product dielectric reliability

Joule heating temperature prediction for inductor

TCAD analysis of breakdown during voltage sweep in a carbon nanofiber (CNF) interconnect

Observation of negative bias temperature instabilities in parasitic p-channel MOSFETs occurring during high-temperature reverse-bias stressing of trench-gated n-channel MOSFETs

Experimental characterization of the interactions between HCI, off-state and BTI degradation modes

Hot Carrier Injection degradation induced dispersion: Model and circuit-level measurement

Spin dependent charge pumping: A new tool for reliability studies

High endurance performance of 1T1R HfOx based RRAM at low (<20μA) operative current and elevated (150°C) temperature

Discussion group summary for IIRW 2011

Special interest group (SIG) summary: Plasma-Induced Damage (PID)

2011 IIRW attendees

Integrated Reliability Workshop

2010 IEEE International Integrated Reliability Workshop Final Report

2009 IEEE International Integrated Reliability Workshop Final Report

2008 IEEE International Integrated Reliability Workshop Final Report

2007 IEEE International Integrated Reliability Workshop Final Report

2006 IEEE International Integrated Reliability Workshop Final Report

2005 IEEE International Integrated Reliability Workshop

IEEE International Integrated Reliability Workshop Final Report, 2004

IEEE International Integrated Reliability Workshop Final Report, 2003

IEEE International Integrated Reliability Workshop Final Report, 2002.

2001 IEEE International Integrated Reliability Workshop. Final Report (Cat. No.01TH8580)

2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)

1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)

1998 IEEE International Integrated Reliability Workshop Final Report (Cat. No.98TH8363)

1997 IEEE International Integrated Reliability Workshop Final Report (Cat. No.97TH8319)

1996 International Integrated Reliability Workshop Final Report

IEEE 1995 International Integrated Reliability Workshop. Final Report

Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS)

International Integrated Reliability Workshop Final Report

Integrated Reliability Workshop

Content Provider	IEEE Xplore Digital Library
Author	Campbell, Jason
Copyright Year	2011
Description	Author affiliation: National Institute of Standards and Technology, 100 Bureau Drive, MS 8120, Gaithersburg, MD 20899 (Campbell, Jason)
Abstract	The IEEE International Integrated Reliability Workshop (IRW) originated from the Wafer Level Reliability Workshop in 1982. The IRW focuses on ensuring electronic device reliability through fabrication, design, testing, characterization, and simulation, as well as identification of the defects and physical mechanisms responsible for reliability problems. Through tutorials, paper presentations, discussion groups, special interest groups, and the informal format of the technical program, a unique environment is provided for understanding, developing, and sharing reliability technology and test methodology for present and future semiconductor applications as well as ample opportunity for discussions and interactions with colleagues. IIRW 2012 will include a special resistive memory invited session. Resistive memory abstract submissions are also encouraged. Additional hot reliability topics for the workshop include: high-K and nitrided SiO2 gate dielectrics, reliability assessment of novel devices, III–V, SOI, emerging memory technologies, transistor reliability including hot carriers and NBTI/PBTI, Cu interconnects and low-k dielectrics, impact of transistor degradation on circuit reliability, reliability modeling and simulation, optoelectronics, and single event upsets. We invite you to submit a presentation proposal that addresses any semiconductor related reliability issue, including the following topics: • Designing-in reliability (products, circuits, systems, processes) • Resistive Memory: Degradation Mechanisms • Deep sub-micron transistor and circuit reliability • Customer product reliability requirements / manufacturer reliability tasks • Root cause defects, physical mechanisms, and simulations • Wafer level reliability tests, test approaches, and reliability test structures
File Size	184985
File Format	PDF
ISBN	9781457701139
ISSN	19308841
e-ISBN	9781457701153
DOI	10.1109/IIRW.2011.6142617
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article

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