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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jun Wu Yiyu Shi Minsu Choi |
| Copyright Year | 2011 |
| Description | Author affiliation: Dept of Electrical & Computer Engineering, Missouri University of Science & Technology Rolla, MO 65409, USA (Jun Wu; Yiyu Shi; Minsu Choi) |
| Abstract | This paper demonstrates a recently proposed low-power side channel attack (SCA) resistant asynchronous S-Box design for the AES crypto-systems. A specified side channel attack standard evaluation FPGA board (SASEBO-GII) is used to implement the design. This board includes two Xilinx FPGAs to perform the cryptographic function and the configuration function separately. This prevents the power trace of the configuration circuit from interfering with the power trace of the cryptographic circuit, so that the measurements of making/resisting power analysis attack can be done fairly. The proposed design is clock free and has flatter power peaks since it is based on a delay-insensitive logic paradigm referred to as null convention logic (NCL). Comparisons between the existing synchronous S-Box design and the proposed asynchronous design are performed in the various aspects; speed, area, total power consumption, and results of differential power analysis (DPA) attack, one of the most powerful cryptanalysis that could extract the secret keys of cryptographic devices. Experimental results shows that the proposed asynchronous S-Box is resistant to DPA attacks and has a lower power consumption than its synchronous counterpart. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 400007 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424479337 |
| ISSN | 10915281 |
| e-ISBN | 9781424479351 |
| DOI | 10.1109/IMTC.2011.5944288 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-05-10 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Power demand Logic gates Power measurement Encryption FPGA implementation Advanced Encryption Standard Substitution Box(S-Box) Side-Channel Attacks(SCA) Differential Power Analysis(DPA) Power/Noise Measurement Null convention logic(NCL) Security |
| Content Type | Text |
| Resource Type | Article |
| Subject | Instrumentation Electrical and Electronic Engineering |
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