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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kyung Ki Kim Jing Huang Yong-Bin Kim Lombardi, F. Minsu Choi |
| Copyright Year | 2007 |
| Description | Author affiliation: Northeastern Univ., Boston (Kyung Ki Kim; Jing Huang; Yong-Bin Kim; Lombardi, F.) |
| Abstract | This paper presents a novel modeling analysis and simulation of jitter for high speed (several gigabit per second) IO channels in VLSI systems. Jitter components are analyzed and modeled individually. The unique features of the components when they are simultaneously injected are identified through simulation. In this work, the effect of settling time on ISI and the relationship among each jitter component are investigated in depth. The validity of superposition of the jitter components is confirmed. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 2457943 |
| Page Count | 4 |
| File Format | |
| ISBN | 1424405882 |
| ISSN | 10915281 |
| DOI | 10.1109/IMTC.2007.379345 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-05-01 |
| Publisher Place | Poland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Analytical models Very large scale integration Intersymbol interference Timing jitter 1f noise Computational modeling Computer simulation Data systems Gaussian distribution Instrumentation and measurement Serial Data Systems Timing Jitter Jitter Components Periodic Jitter Random Jitter Inter-Symbol Interference Duty Cycle Distortion |
| Content Type | Text |
| Resource Type | Article |
| Subject | Instrumentation Electrical and Electronic Engineering |
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