NDLI: A novel architecture for a massively parallel low level vision processing engine on chip

Content Provider	IEEE Xplore Digital Library
Author	Tomasi, M. Vanegas, M. Barranco, F. Diaz, J. Ros, E.
Copyright Year	2010
Description	Author affiliation: Computer Architecture and Tecnology Department, University of Granada, Spain (Tomasi, M.; Vanegas, M.; Barranco, F.; Diaz, J.; Ros, E.)
Abstract	Specific architectures for different low level vision modalities have been developed and described using reconfigurable hardware. Each of them tries to solve a single low level vision problem: optical flow, disparity, segmentation, tracking, etc. We introduce a novel architecture that includes multiple processing engines in a massively parallel low level vision processing engine of very high complexity and performance. Our design is able to process input images and extract at the same time different visual features such as multi-scale stereo, optical flow and local contrast descriptors such as local orientation, energy or phase. The latest hardware design techniques have been employed in order to achieve the presented system with more than 2000 basic processing elements running in parallel. We have based our system in a Harmonic filter image decomposition model based on Gabor-like filters. It has been validated in multiple scenarios in previous works and it allows sharing hardware resources among different vision modalities on the same chip. In this paper we present an FPGA based implementation of this intensive processing engine as well as the designing techniques employed. The circuit processes input frames of 512×512 pixels at 28 frames per second.
Starting Page	3033
Ending Page	3039
File Size	1118675
Page Count	7
File Format	PDF
ISBN	9781424463909
e-ISBN	9781424463923
DOI	10.1109/ISIE.2010.5637211
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-04
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optical imaging Hardware Pixel Computer architecture Clocks Engines Feature extraction
Content Type	Text
Resource Type	Article

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