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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jing Zhong Muzio, J.C. |
| Copyright Year | 2006 |
| Description | Author affiliation: Victoria Univ., Victoria (Jing Zhong) |
| Abstract | Reversible logic computing is a rapidly developing research area. Testing such circuits is obviously an important issue. In this paper, we consider a new fault model, labeled crosspoint faults, for reversible logic circuits. A randomized Automatic Test Pattern Generation algorithm targeting this specific kind of fault is introduced and analyzed. Simulation results show that the algorithm yields very good performance. The relationship between the crosspoint faults and stuck-at faults is also investigated. We show that the crosspoint fault model is a better fault model for reversible circuits since it dominates the traditional stuck-at fault model in most instances. |
| Starting Page | 2422 |
| Ending Page | 2427 |
| File Size | 236497 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780394879 |
| DOI | 10.1109/CEC.2006.1688609 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-07-16 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit faults Logic circuits Circuit testing Automatic test pattern generation Programmable logic arrays Logic testing Circuit simulation Physics computing Quantum computing Performance evaluation |
| Content Type | Text |
| Resource Type | Article |
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