NDLI: Optimized Memory Assignment for DSPs

Content Provider	IEEE Xplore Digital Library
Author	Grewal, G. Coros, S. Banerji, D. Morton, A. Ventresca, M.
Copyright Year	2006
Description	Author affiliation: Department of Computing and Information Science, University of Guelph, Guelph, ON, Canada, N1G 2W1 (Grewal, G.)
Abstract	To increase memory bandwidth, many programmable Digital Signal Processors (DSPs) employ two on-chip data memories. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to occur in parallel. Exploiting dual memory banks, however, is a challenging problem for compilers. This, in part, is due to the instruction-level parallelism, small numbers of registers, and highly specialized register capabilities of most DSPs. In this paper, we present a new methodology based on a genetic algorithm for assigning data to dual-bank memories. Our approach is global, and integrates several important issues in memory assignment within a single model. Special effort is made to identify those data objects that could potentially benefit from an assignment to a specific memory, or perhaps duplication in both memories. Our computational results show that the GA is able to achieve a 54% reduction in the number of memory cycles and a reduction in the range of 7% to 42% in the total number of cycles when tested with well-known DSP kernels and applications.
Starting Page	64
Ending Page	72
File Size	270116
Page Count	9
File Format	PDF
ISBN	0780394879
DOI	10.1109/CEC.2006.1688291
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-16
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Registers Bandwidth Parallel processing Genetic algorithms Information science Digital signal processors Testing Kernel Application software
Content Type	Text
Resource Type	Article

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