NDLI: Design of combinational logic training system using FPGA

Content Provider	IEEE Xplore Digital Library
Author	Sothong, S. Chayratsami, P.
Copyright Year	2010
Description	Author affiliation: King Mongkut Institute of Technology Ladkrabang (Sothong, S.; Chayratsami, P.)
Abstract	This paper describes a design of a training system for a combinational logic design course. The goals of this design are to reduce a cost of the system and to lower the lost and damage of TTL elements used in a digital laboratory currently. The system uses a Field Programmable Gate Array (FPGA) as a processor containing basic logic gates, and uses a microcontroller as a gate selector. The training system consists of a system unit base, 17 basic logic gate models, and 10 lab sheets. The system is evaluated in terms of quality and using suitability of the system by experts and instructors who work with technical schools in Thailand and have been involving and teaching a combinational logic design course for at least 5 years. The results show that the system is rated to have a very good quality and is suitable for being used as a training system in a combinational logic course with inexpensive cost.
File Size	1268165
File Format	PDF
ISBN	9781424462612
ISSN	01905848
e-ISBN	9781424462629
e-ISBN	9781424462605
DOI	10.1109/FIE.2010.5673663
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Training Integrated circuit modeling Logic gates Laboratories Field programmable gate arrays Switches training system Combinational Logic design FPGA laboratory
Content Type	Text
Resource Type	Article
Subject	Education Computer Science Applications Software

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