NDLI: Design of an on-line IEEE floating-point addition unit for FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Krueger, S.D. Seidel, P.-M.
Copyright Year	2004
Description	Author affiliation: Texas Instrum. Inc., Dallas, TX, USA (Krueger, S.D.)
Abstract	We present the design of an on-line IEEE floating-point (FP) adder. In on-line arithmetic a result is computed as a digit serial output stream from digit serial input streams. The result digits begin to be produced a short delay after the first input digits arrive and before all the input digits have been received. On-line arithmetic proceeds from the most significant digit first through the least significant digit. Performing on-line addition on IEEE FP numbers imposes challenges beyond the challenges of conventional on-line arithmetic, including the task of normalization and IEEE rounding and its effect on the digits already output. The proposed implementations are very suitable for FPGAs, because the serial organization simplifies critical components of conventional FPGA IEEE FP addition implementations: Large alignment and normalization shifters are avoided allowing for reduced interconnection complexities and reasonable latencies at low implementation cost. The proposed implementations are fully compliant with the IEEE FP standard.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on Comput. Archit
Starting Page	239
Ending Page	246
File Size	284275
Page Count	8
File Format	PDF
ISBN	0769522300
DOI	10.1109/FCCM.2004.28
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Floating-point arithmetic Delay Costs Fixed-point arithmetic Hardware Reconfigurable logic Transistors Clocks Frequency on-line arithmetic Floating-point addition IEEE rounding
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scalable and modular algorithms for floating-point matrix multiplication on FPGAs

On-line IEEE floating-point multiplication and division for reduced power dissipation

Architectural Modifications to Enhance the Floating-Point Performance of FPGAs

Higher radix floating-point representations for FPGA-based arithmetic

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

Floating-Point Divider Design for FPGAs

A Study on the Floating-Point Adder in FPGAS

Efficient floating-point logarithm unit for FPGAs

Open Source High Performance Floating-Point Modules

Design of an on-line IEEE floating-point addition unit for FPGAs

Similar Documents

Scalable and modular algorithms for floating-point matrix multiplication on FPGAs

On-line IEEE floating-point multiplication and division for reduced power dissipation

Architectural Modifications to Enhance the Floating-Point Performance of FPGAs

Higher radix floating-point representations for FPGA-based arithmetic

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

Floating-Point Divider Design for FPGAs

A Study on the Floating-Point Adder in FPGAS

Efficient floating-point logarithm unit for FPGAs

Open Source High Performance Floating-Point Modules

Design of an on-line IEEE floating-point addition unit for FPGAs