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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lee, D.-U. Luk, W. Wang, C. Jones, C. |
| Copyright Year | 2004 |
| Description | Author affiliation: Dept. of Comput., Imperial Coll., London, UK (Lee, D.-U.; Luk, W.) |
| Abstract | We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve better performance and lower decoding complexity than turbo codes, a major drawback of LDPC codes is their apparently high encoding complexity. Using an efficient encoding method proposed by Richardson and Urbanke, we present a hardware LDPC encoder with linear encoding complexity. The encoder is flexible, supporting arbitrary H matrices, rates and block lengths. An implementation for a rate 1/2 irregular length 2000 LDPC code encoder on a Xilinx Virtex-II XC2V4000-6 FPGA takes up 4% of the device. It runs at 143 MHz and has a throughput of 45 million codeword bits per second (or 22 million information bits per second) with a latency of 0.18 ms. The performance can be improved by exploiting parallelism: several instances of the encoder can be mapped onto the same chip to encode multiple message blocks concurrently. An implementation of 16 instances of the encoder on the same device at 82 MHz is capable of 410 million codeword bits per second, 80 times faster than an Intel Pentium-lV 2.4 GHz PC. |
| Sponsorship | IEEE Comput. Soc. Tech. Comm. on Comput. Archit |
| Starting Page | 101 |
| Ending Page | 111 |
| File Size | 426015 |
| Page Count | 11 |
| File Format | |
| ISBN | 0769522300 |
| DOI | 10.1109/FCCM.2004.4 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-04-20 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Parity check codes Turbo codes Forward error correction Decoding Throughput Sparse matrices Educational institutions Field programmable gate arrays Delay |
| Content Type | Text |
| Resource Type | Article |
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