NDLI: Large area flexible electronics for analog mode continuous time applications

Content Provider	IEEE Xplore Digital Library
Author	Raghuraman, M. Sambandan, S. Yadav, S.
Copyright Year	2015
Description	Author affiliation: Dept. of Instrum. & Appl. Phys., Indian Inst. of Sci., Bangalore, India (Raghuraman, M.; Sambandan, S.) \|\| Dept. of Mater. Eng., Indian Inst. of Sci., Bangalore, India (Yadav, S.)
Abstract	Conventionally, the applications of non-crystalline semiconductor based Thin Film Transistors (TFTs) are confined to large area display applications. Typically they are used in the driver circuits of pixel arrays. One of the fundamental characteristics of such TFTs is the drift in the threshold voltage VT on application of gate bias. This paper presents a novel circuit simulator based on the recursive model of VT shift and shows how the simulator can be used to explore novel analog mode continuous time applications of TFTs based on sensor actuator architectures. While operating in analog mode, VT shift causes the DC operating point of the circuit to vary. Using this circuit simulator, the concept of employing negative feedback to minimize the drain current variation in circuits made of TFTs is studied. The ideas are validated by fabricating p-type Copper phthalocyanine (CuPC) TFTs and testing the circuits.
Starting Page	1
Ending Page	6
File Size	1143663
Page Count	6
File Format	PDF
e-ISBN	9781479999859
DOI	10.1109/CONECCT.2015.7383892
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling MOSFET Threshold voltage shift Computational modeling TFTs Large Area Flexible Electronics Logic gates Threshold voltage Thin film transistors Bias stress Integrated circuit modeling Simulator
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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