NDLI: Energy-efficient femtocell placement in LTE networks

Content Provider	IEEE Xplore Digital Library
Author	Ramamurthy, A. Sathya, V. Venkatesh, V. Ramji, R. Tamma, B.R.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Hyderabad, Hyderabad, India (Ramamurthy, A.; Sathya, V.; Venkatesh, V.; Ramji, R.; Tamma, B.R.)
Abstract	To enhance battery life of mobile handsets and increase the data rates for indoor users in LTE networks, low power nodes like Femtos are deployed in homes and enterprise buildings. But the optimal placement of Femtos is a challenging task due to heterogeneity in building layouts and co-tier intercell interference. In this work, we focus on reducing the battery power consumption (uplink transmit power) while guaranteeing uplink Signal to Interference plus Noise Ratio (SINR) threshold (USINRTh) and downlink SINR threshold (DSINRTh). We achieve this by placing the Femtos optimally, taking into account wall attenuation factor and interference among Macro and Femto base stations. A two-step optimization model has been formulated: in step one, we formulate a Mixed Integer Programming (MIP) problem yields the optimal positions of the Femtos and meets DSINRTh and USNRTh while also minimizing Femto count and uplink transmission power. In step two, we formulate a Linear Programming (LP) problem with the aim of guaranteeing USINRTh and minimizing the total uplink power, after placing the Femtos in the optimal positions obtained from step one. When compared to center K-means placement scheme, the proposed optimal placement scheme obtained by solving the two-step model registers a significant, 47%, reduction in uplink energy consumption.
Starting Page	1
Ending Page	6
File Size	270962
Page Count	6
File Format	PDF
e-ISBN	9781479999859
DOI	10.1109/CONECCT.2015.7383858
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Buildings Interference Downlink Batteries Uplink Optimization Signal to noise ratio
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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