NDLI: 1–7 GHz wideband low loss SPDT switch MMIC

Content Provider	IEEE Xplore Digital Library
Author	Verma, P. Kumar, A. Bhattacharya, A.N. Arora, R.
Copyright Year	2015
Description	Author affiliation: Space Applic. Centre, Indian Space Res. Organ., Ahmedabad, India (Verma, P.; Kumar, A.; Bhattacharya, A.N.; Arora, R.)
Abstract	A low loss wideband (1-7GHz) SPDT switch using 0.13μm GaAs/InAlAs MHEMT MMIC process is designed, fabricated and tested both on-wafer and in test fixture. The measured results are in close agreement with specifications and simulations, which exhibit insertion loss of 1.05 ±0.05dB, with isolation of 28dB, minimum. All three ports of this SPDT switch are well matched having return loss of more than 14 dB because of series-shunt topology. A series capacitor is also introduced in the common arm working as a DC block. The simulated 1-dB compression takes place at input power of more than +18dBm at 7 GHz and IIP3 is better than +33.5dBm. Being gate voltages of -1.5V and 0V, negligible (<;1mW) power is consumed while operating this switch. This SPDT switch measuring less than 1 mm2 in area enables on chip integration with high performance redundant Ka-band down-converter system-on-chip (SoC). Low loss, high isolation, compactness are the key features of this switch MMIC.
Starting Page	1
Ending Page	4
File Size	406743
Page Count	4
File Format	PDF
e-ISBN	9781479999859
DOI	10.1109/CONECCT.2015.7383880
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistors HEMT Redundancy Switches Insertion loss Logic gates HEMTs MMICs Loss measurement System-on-chip
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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