NDLI: Enhancement of Wishbone protocol with broadcasting and multicasting

Content Provider	IEEE Xplore Digital Library
Author	Agarwal, Gourav Ramesh Kini M.
Copyright Year	2015
Description	Author affiliation: Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Mangalore, 575025, India (Agarwal, Gourav; Ramesh Kini M.)
Abstract	Wishbone is a standard System-on-Chip (SoC) bus interface for Intellectual Property (IP) core modules to communicate with each other. The present day SoCs have large number of interconnected cores/processing-elements (PE) that need to communicate with each other. Typical scenario would have a Master processor/Controller-Core and large number of Slave/hardware-accelerator/co-processor/PE cores. These cores may have their own local private memory and may share memory blocks with other cores. The cores need to transfer data/instructions between themselves, peripherals and input-output ports. In case of applications demanding Single-Kernel-Multiple-Data (SKMD), the Controller core may transfer the common kernel-code to PEs using Broadcast or Multicast technique rather than transmitting the same kernel-code multiple times. Similarly the controller core can transfer the common data to multiple cores using Broadcast or Multicast technique in the case of Multiple-Kernel-Single-Data (MKSD). In this paper, it is exhibited that Wishbone protocol capability can be enhanced by including Multicasting and Broadcasting features. Promising results have been achieved with simulation and synthesis of the whole module on Xilinx 14.4 ISE platform. Design has been implemented on Xilinx FPGA platform using Nexys-4 (Artix-7) board.
Starting Page	1
Ending Page	5
File Size	65015
Page Count	5
File Format	PDF
e-ISBN	9781479999859
DOI	10.1109/CONECCT.2015.7383856
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	IEEE Xplore Portable document format SKMD MKSD Master Multicast Wishbone Slave Coprocessor Broadcast Processing-Elements Arbiter Controller core Hardware-Accelerator
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Enhancement of Wishbone protocol with broadcasting and multicasting