NDLI: VLSI implementation of sliding window DFT

Content Provider	IEEE Xplore Digital Library
Author	Chandrakanth, V. Devendranath, C. Shamnar, A.
Copyright Year	2013
Description	Author affiliation: Defense R&D Lab., DRDO, Hyderabad, India (Chandrakanth, V.; Devendranath, C.; Shamnar, A.)
Abstract	Sliding DFT analysis is done to calculate the spectrum of the input signal on sample by sample basis. It is very effective technique available to identify the random and abrupt faults in the input data. Spikes constrained in time domain data are spread out in frequency domain corrupting the frequency data and in some cases masking the weak signal in adjacent frequency bins. Using sliding DFT we can isolate the spike from input data or recognize the occurrence and take necessary processing precautions preventing the corrupted data to be passed on for further processing. The sudden discontinuity is identified by sudden increase in side lobe levels of the Doppler filter bank. The effect of the disturbance persists for data length of `2N -1'. But by setting appropriate thresholds it can be identified and can be isolated. In this paper we present hardware architecture to perform the sliding window DFT on FPGA. The architecture is difficult to implement using vendor supplied IP cores as they are designed to work for block input and not by sample by sample data flow. In block data flow it can be identified but cannot be resolved precisely. And since there is no provision to access the twiddle factors in IP cores which form the crux of FFT processing, SDFT realized using IP cores cannot be further optimized thus reducing its configurability. To achieve sliding DFT we have designed customized and configurable DFT block and structured the data flow using memory arrays to realize sliding window operation.
Sponsorship	IEEE India Council ED Chapter
Starting Page	258
Ending Page	262
File Size	558518
Page Count	5
File Format	PDF
ISBN	9781467348614
e-ISBN	9781467348621
DOI	10.1109/ICSIPR.2013.6497934
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency-domain analysis IP core Discrete Fourier transforms FPGA FIR FFT Signal processing algorithms Computer architecture Twiddle Factors SDFT IP networks Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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