NDLI: IP core based architecture of telecommand System-on-Chip (SoC) for spacecraft applications

Content Provider	IEEE Xplore Digital Library
Author	Rajesvari, R. Manoj, G. Ponrani, M.A. Joy, M.A.
Copyright Year	2013
Description	Author affiliation: Dept. of ECE, Karunya Univ., Coimbatore, India (Rajesvari, R.; Manoj, G.; Ponrani, M.A.; Joy, M.A.)
Abstract	Consumer demands for high performance and rich functionality have driven the semiconductor manufacturing industry to the integration of multiple complex components onto a single chip. As the complexity of the remotely located physical devices increases, the requirement for a greater telecommanding capability and efficiency arises. This is achieved by embedding pre-designed functions into a single SoC, which utilizes specialized reusable core (IP cores) architecture into complex chip.This paper is concerned with the design of telecommand system for transfer of signals from ground station to space station by the integration of SRAM(Static Random Access Memory), ARM (Advanced RISC Machine) Processor, EDAC unit (Error Detection And Correction). The results are analysed for SPARTAN 3, SPARTAN 6, VIRTEX 4 and VIRTEX 5 FPGA devices. The IP core based architecture using VIRTEX 5 FPGA device makes a trade-off between frequency and time delay with 48% increase in operating frequency and having a minimum time delay of about 5%.
Sponsorship	IEEE India Council ED Chapter
Starting Page	163
Ending Page	168
File Size	786433
Page Count	6
File Format	PDF
ISBN	9781467348614
e-ISBN	9781467348621
DOI	10.1109/ICSIPR.2013.6497979
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	IP cores Random access memory EDAC unit ARM Processor Registers Table lookup IP networks Arrays SRAM Standards Telecommand
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

SRAM based longest prefix matching approach for multigigabit IP processing

The Study of SoC Architecture Design Based on 32-bit Embedded RISC Processor

Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Implementation of extended Open Core Protocol interface memory system using Verilog HDL

On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks

A prototyping IP for mobile computing SOC

Implementation of an Arm Compatible Processor Core for SOC Designs

Architecture and performance models for scalable IP lookup engines on FPGA

DES-SRAM IP-core: a SRAM embedding DES feature [secure SoC applications]

IP core based architecture of telecommand System-on-Chip (SoC) for spacecraft applications

Similar Documents

SRAM based longest prefix matching approach for multigigabit IP processing

The Study of SoC Architecture Design Based on 32-bit Embedded RISC Processor

Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Implementation of extended Open Core Protocol interface memory system using Verilog HDL

On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks

A prototyping IP for mobile computing SOC

Implementation of an Arm Compatible Processor Core for SOC Designs

Architecture and performance models for scalable IP lookup engines on FPGA

DES-SRAM IP-core: a SRAM embedding DES feature [secure SoC applications]

IP core based architecture of telecommand System-on-Chip (SoC) for spacecraft applications