NDLI: A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique

Content Provider	IEEE Xplore Digital Library
Author	Pin-Tseng Chen Chia-Chen Chang Han-Ying Liu Yu-Lung Lo
Copyright Year	2012
Abstract	In this paper, a fast-lock analog delay-locked loop (DLL) using the dual-slope technique is presented. The architecture of the proposed DLL uses an improved charge pump and two kinds of the phase detector to achieve faster locking time, smaller area cost, and better jitter performance. The DLL was designed using a 0.35 µm standard CMOS process with a 3.3V supply voltage. The simulation results show that the proposed DLL can be operated correctly when the input clock frequency is changed from 140 MHz to 270 MHz and generate equally spaced eight-phase clocks. When the input clock frequency is 230 MHz, the peak-to-peak jitter is 3.2 ps and the static phase error is 4.1 ps. Moreover, the locking time is 88 clock cycles, the power consumption is 10.8 mW, and core area is 0.069 mm2.
Starting Page	954
Ending Page	957
File Size	1050165
Page Count	4
File Format	PDF
ISBN	9781467307673
DOI	10.1109/IS3C.2012.249
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-04
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Partial discharges Charge pumps Analog DLL Fast Lock Phase frequency detector Multiphase Jitter Low Jitter Dual Slope. Phase locked loops Delay Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Fast-Lock Analog Multiphase Delay-Locked Loop Using a Dual-Slope Technique